Search results for "Twiddle factor"

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Area-efficient FPGA-based FFT processor

2003

A novel architecture for computing the fast Fourier transform on programmable devices is presented. Main results indicate that the use of one CORDIC operator to perform the multiplication by all the ‘twiddle factors’ sequentially leads to an area saving up to 35% with respect to other cores.

Cooley–Tukey FFT algorithmSplit-radix FFT algorithmComputer sciencebusiness.industryFast Fourier transformPrime-factor FFT algorithmMultiplicationElectrical and Electronic EngineeringCORDICField-programmable gate arraybusinessTwiddle factorComputer hardwareElectronics Letters
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